论文标题
C-and：混合写作方案，用于减少1T铁电的FET记忆
C-AND: Mixed Writing Scheme for Disturb Reduction in 1T Ferroelectric FET Memory
论文作者
论文摘要
铁电场效应晶体管（FEFET）记忆表明，有可能满足对快速，密集，低功率和非易失性记忆需求不断增长的需求的潜力。在本文中，我们提出了一个名为Crossed and（c-and）的内存架构，其中每个存储单元由单个铁电晶体管组成。使用不同的写入方案和不同的绝对电压执行写操作，以说明FEFET的不对称开关电压。它使得在两个连续的周期中写下整个文字线，并通过晶体管的通道来防止当前和功率。在读取操作过程中，电流和功率主要在每列中的单个选定设备上感测。读取方案还使阅读整个单词无需读取错误即使是沿着长的位线。我们的模拟表明，与先前提出的和架构相比，C-and体系结构减少了读取错误，减少写入干扰，实现较长的位点的用法，并在存储单元区域中最多保存2.92倍。
Ferroelectric field effect transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low-power, and non-volatile memories. In this paper, we propose a memory architecture named crossed-AND (C-AND), in which each storage cell consists of a single ferroelectric transistor. The write operation is performed using different write schemes and different absolute voltages, to account for the asymmetric switching voltages of the FeFET. It enables writing an entire wordline in two consecutive cycles and prevents current and power through the channel of the transistor. During the read operation, the current and power are mostly sensed at a single selected device in each column. The read scheme additionally enables reading an entire word without read errors, even along long bitlines. Our Simulations demonstrate that, in comparison to the previously proposed AND architecture, the C-AND architecture diminishes read errors, reduces write disturbs, enables the usage of longer bitlines, and saves up to 2.92X in memory cell area.
