论文标题
密码学中非常大的恒定乘法的无乘数设计
Multiplierless Design of Very Large Constant Multiplications in Cryptography
论文作者
论文摘要
本简介解决了使用最小数量的加法器/减法器在Shift-Adds体系结构下通过单个变量实现非常大的恒定乘法的问题。由于问题的固有复杂性，我们引入了一种近似算法，称为tõll，该算法将非常大的常数分解为较小的常数。为了减少操作数量，T 3将结合基于图的和常见的子表达消除方法，该方法为恒定乘法的偏移设计设计。它还可以考虑根据串联操作的最大操作数量（即adder steps的数量，同时减少操作数量）定义的无乘数延迟。高级实验结果表明，随着操作数量的开销，可以显着降低Shift-Adds设计的加法步骤。栅极级别的实验结果表明，尽管使用乘数相对于设计，但与区域瓦的优化相比，相对于设计的设计，相对于设计的设计可能会导致栅极级别面积减少36.6 \％\％降低，但延迟吸引的优化可以减少48.3％的降低。
This brief addresses the problem of implementing very large constant multiplications by a single variable under the shift-adds architecture using a minimum number of adders/subtractors. Due to the intrinsic complexity of the problem, we introduce an approximate algorithm, called TÕLL, which partitions the very large constants into smaller ones. To reduce the number of operations, TÕLL incorporates graph-based and common subexpression elimination methods proposed for the shift-adds design of constant multiplications. It can also consider the delay of a multiplierless design defined in terms of the maximum number of operations in series, i.e., the number of adder-steps, while reducing the number of operations. High-level experimental results show that the adder-steps of a shift-adds design can be reduced significantly with a little overhead in the number of operations. Gate-level experimental results indicate that while the shift-adds design can lead to a 36.6\% reduction in gate-level area with respect to a design using a multiplier, the delay-aware optimization can yield a 48.3\% reduction in minimum achievable delay of the shift-adds design when compared to the area-aware optimization.
