论文标题
在数字通信接收器中进行时间交织的ADC的新型基于错误的背景校准的设计和实验验证
Design and Experimental Verification of a Novel Error-Backpropagation-Based Background Calibration for Time Interleaved ADC in Digital Communication Receivers
论文作者
论文摘要
本文介绍了一种新型的背景校准技术，用于时间间隔的类似物到数字转换器（TI-ADC）。该技术适用于均衡的数字通信接收器。如Tsai等人所示。 [1]和Luna等。 [2]，在数字接收器中，可以将TI-ADC错误作为通信渠道的一部分，并利用自适应均衡器来补偿它们。因此，校准成为通道均衡的组成部分。不需要特殊目的模拟或数字校准块或算法。但是，由于其他信号处理块位于TI-ADC和均衡器之间，因此有大量的接收器无法直接应用均衡技术。这里提出的技术将早期的作品推广到此类的接收器。传统上用于机器学习的错误反向传播算法应用于在接收器切片机处计算的误差，并用于调整与Ti-ADC相邻的辅助均衡器，称为补偿均衡器（CE）。使用双极化光学相干接收器模型的仿真显示了在不同的应用方案中的准确和稳健的不匹配补偿。在模拟中测试了几个正交振幅调制（QAM）方案，并通过实验进行测试。仿真平台上的测量值包括在130nm CMOS技术中制造的8位，4 GS/S TI-ADC原型芯片，在测试了64-QAM和256-QAM方案时，对不匹配对接收器性能的影响几乎是理想的缓解措施。测量了SNDR和SFDR中$ \ sim $ 15 dB的TI-ADC性能的绝对改善。
A novel background calibration technique for Time-Interleaved Analog-to-Digital Converters (TI-ADCs) is presented in this paper. This technique is applicable to equalized digital communication receivers. As shown by Tsai et al. [1] and Luna et al. [2], in a digital receiver it is possible to treat the TI-ADC errors as part of the communication channel and take advantage of the adaptive equalizer to compensate them. Therefore calibration becomes an integral part of the channel equalization. No special purpose analog or digital calibration blocks or algorithms are required. However, there is a large class of receivers where the equalization technique cannot be directly applied because other signal processing blocks are located between the TI-ADC and the equalizer. The technique presented here generalizes earlier works to this class of receivers. The error backpropagation algorithm, traditionally used in machine learning, is applied to the error computed at the receiver slicer and used to adapt an auxiliary equalizer adjacent to the TI-ADC, called the Compensation Equalizer (CE). Simulations using a dual polarization optical coherent receiver model demonstrate accurate and robust mismatch compensation across different application scenarios. Several Quadrature Amplitude Modulation (QAM) schemes are tested in simulations and experimentally. Measurements on an emulation platform which includes an 8 bit, 4 GS/s TI-ADC prototype chip fabricated in 130nm CMOS technology, show an almost ideal mitigation of the impact of the mismatches on the receiver performance when 64-QAM and 256-QAM schemes are tested. An absolute improvement in the TI-ADC performance of $\sim$15 dB in both SNDR and SFDR is measured.
