论文标题
Chiplet精算师：定量成本模型和多芯片架构探索
Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration
论文作者
论文摘要
多芯片整合被广泛认为是摩尔定律的扩展。节省成本是经常提到的优势，但以前的作品很少出现关于多芯片整合比单片SOC的成本优势的定量演示。在本文中，我们建立了一个定量成本模型，并根据三种典型的多芯片集成技术提出了一种分析方法，以分析提高产量，chiplet和套件重复使用以及异质性的成本收益。我们从各个角度重新检查了多芯片系统的实际成本，并通过适当的多芯片体系结构展示了如何降低VLSI系统的总成本。
Multi-chip integration is widely recognized as the extension of Moore's Law. Cost-saving is a frequently mentioned advantage, but previous works rarely present quantitative demonstrations on the cost superiority of multi-chip integration over monolithic SoC. In this paper, we build a quantitative cost model and put forward an analytical method for multi-chip systems based on three typical multi-chip integration technologies to analyze the cost benefits from yield improvement, chiplet and package reuse, and heterogeneity. We re-examine the actual cost of multi-chip systems from various perspectives and show how to reduce the total cost of the VLSI system through appropriate multi-chiplet architecture.
