论文标题

使用FPGA对自主系统的实时正式验证

Real-Time Formal Verification of Autonomous Systems With An FPGA

论文作者

Bui, Minh, Lu, Michael, Hojabr, Reza, Chen, Mo, Shriraman, Arrvindh

论文摘要

汉密尔顿 - 雅各比(Hamilton-Jacobi)的可达性分析是一种强大的技术,用于验证自主系统的安全性。此方法非常擅长处理非线性系统动力学,并具有干扰和灵活的设置表示。这种方法的缺点是它遭受了维度的诅咒,从而阻止了对安全至关重要系统的实时部署。在本文中,我们表明,在现场可编程门阵列(FPGA)上进行定制的硬件设计可以加速基于4D网格的汉密尔顿 - 雅各布(HJ)可及性分析,而与优化的实现相比,与16线ReadCPU上的MATLAB工具箱相比,最多可加速16次。我们的设计可以克服复杂的数据访问模式,同时利用HJ PDE计算的平行性质。因此,我们能够通过4D CAR模型来实现实时正式验证,通过随着环境的变化,FPGA上的5Hz频率将HJ PDE重新溶解。我们计算的延迟是确定性的,这对于安全关键系统至关重要。我们此处介绍的方法可以应用于不同的系统动力学,此外,有可能利用用于更高维度的系统。在不断变化的环境中,我们还可以用机器人车避免障碍物。

Hamilton-Jacobi reachability analysis is a powerful technique used to verify the safety of autonomous systems. This method is very good at handling non-linear system dynamics with disturbances and flexible set representations. A drawback to this approach is that it suffers from the curse of dimensionality, which prevents real-time deployment on safety-critical systems. In this paper, we show that a customized hardware design on a Field Programmable Gate Array (FPGA) could accelerate 4D grid-based Hamilton-Jacobi (HJ) reachability analysis up to 16 times compared to an optimized implementation and 142 times compared to MATLAB ToolboxLS on a 16-thread CPU. Our design can overcome the complex data access pattern while taking advantage of the parallel nature of the HJ PDE computation. Because of this, we are able to achieve real-time formal verification with a 4D car model by re-solving the HJ PDE at a frequency of 5Hz on the FPGA as the environment changes. The latency of our computation is deterministic, which is crucial for safetycritical systems. Our approach presented here can be applied to different systems dynamics, and moreover, potentially leveraged for higher dimensions systems. We also demonstrate obstacle avoidance with a robot car in a changing environment.

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