论文标题
低延迟异步逻辑设计用于边缘的推理
Low-Latency Asynchronous Logic Design for Inference at the Edge
论文作者
论文摘要
现代物联网（IoT）设备使用感知的数据在设备上利用机器学习推断，而不是将它们卸载到云中。通常被称为“边缘推理”，这给用户带来了许多好处，包括个性化和安全性。但是，这种应用需要高能源效率和鲁棒性。在本文中，我们提出了一种使用学习自动机原理设计的自切定时早期促进异步推理电路的区域和电源开销的方法。由于对时间安排的自然韧性以及逻辑上的基础，这些电路对环境和供应电压的变化耐受性，同时可以实现最低的潜伏期。我们的方法通过推理数据stath来举例说明低功率机学习应用程序。该电路以Tsetlin Machine算法为基础，进一步提高了其能源效率。与同步实现相比，所提出的电路的平均延迟减少了10倍，同时保持相似的区域。拟议电路的鲁棒性通过在0.25 V至1.2 V电源的合成后模拟证明。保持功能正确性，并随着电压降低而随栅极延迟的延迟尺度。
Modern internet of things (IoT) devices leverage machine learning inference using sensed data on-device rather than offloading them to the cloud. Commonly known as inference at-the-edge, this gives many benefits to the users, including personalization and security. However, such applications demand high energy efficiency and robustness. In this paper we propose a method for reduced area and power overhead of self-timed early-propagative asynchronous inference circuits, designed using the principles of learning automata. Due to natural resilience to timing as well as logic underpinning, the circuits are tolerant to variations in environment and supply voltage whilst enabling the lowest possible latency. Our method is exemplified through an inference datapath for a low power machine learning application. The circuit builds on the Tsetlin machine algorithm further enhancing its energy efficiency. Average latency of the proposed circuit is reduced by 10x compared with the synchronous implementation whilst maintaining similar area. Robustness of the proposed circuit is proven through post-synthesis simulation with 0.25 V to 1.2 V supply. Functional correctness is maintained and latency scales with gate delay as voltage is decreased.
