论文标题
在安全深度学习加速器中密封神经网络模型
SEALing Neural Network Models in Secure Deep Learning Accelerators
论文作者
论文摘要
深度学习(DL)加速器越来越多地部署在边缘设备上,以支持快速的本地推断。但是,他们遭受了一个新的安全问题,即容易受到基于物理访问的攻击的影响。对手可以通过物理窥探将加速器芯片与DRAM内存连接的GDDR存储总线来轻松获取整个神经网络(NN)模型。因此,内存加密对于边缘设备上的DL加速器而言很重要,以提高NN模型的安全性。然而,我们观察到,在DL加速器中直接使用时,在CPU系统中有效使用的传统内存加密解决方案会导致大量性能降解。主要原因来自GDDR内存总线和加密引擎之间的巨大带宽差距。为了解决这个问题,我们的论文提出了SEAL,这是一种安全有效的加速器方案,用于深度学习。密封从两个方面增强了加密DL加速器的性能,即提高数据访问带宽和内存加密效率。具体而言,为了改善数据访问带宽,密封利用了一个关键的智能加密方案,该方案识别了对NN模型安全性没有影响的部分数据,并允许他们绕过加密引擎,从而减少了要加密的数据。为了提高内存加密的效率,密封利用托管模式加密方案来消除通过共同储存数据及其计数器来消除用于加密的计数器的内存访问。我们的实验结果表明,与传统的记忆加密解决方案相比,密封量可实现1.4〜1.6倍的IPC改进,并将推断潜伏期降低39%〜60%。与没有内存加密的基线加速器相比,SEAL仅损害了5%〜7%IPC,以进行大幅改进。
Deep learning (DL) accelerators are increasingly deployed on edge devices to support fast local inferences. However, they suffer from a new security problem, i.e., being vulnerable to physical access based attacks. An adversary can easily obtain the entire neural network (NN) model by physically snooping the GDDR memory bus that connects the accelerator chip with DRAM memory. Therefore, memory encryption becomes important for DL accelerators on edge devices to improve the security of NN models. Nevertheless, we observe that traditional memory encryption solutions that have been efficiently used in CPU systems cause significant performance degradation when directly used in DL accelerators. The main reason comes from the big bandwidth gap between the GDDR memory bus and the encryption engine. To address this problem, our paper proposes SEAL, a Secure and Efficient Accelerator scheme for deep Learning. SEAL enhances the performance of the encrypted DL accelerator from two aspects, i.e., improving the data access bandwidth and the efficiency of memory encryption. Specifically, to improve the data access bandwidth, SEAL leverages a criticality-aware smart encryption scheme which identifies partial data that have no impact on the security of NN models and allows them to bypass the encryption engine, thus reducing the amount of data to be encrypted. To improve the efficiency of memory encryption, SEAL leverages a colocation mode encryption scheme to eliminate memory accesses from counters used for encryption by co-locating data and their counters. Our experimental results demonstrate that, compared with traditional memory encryption solutions, SEAL achieves 1.4 ~ 1.6 times IPC improvement and reduces the inference latency by 39% ~ 60%. Compared with a baseline accelerator without memory encryption, SEAL compromises only 5% ~ 7% IPC for significant security improvement.