论文标题

随机的最后一个级缓存仍然容易受到缓存侧通道攻击的攻击!但是我们可以解决

Randomized Last-Level Caches Are Still Vulnerable to Cache Side-Channel Attacks! But We Can Fix It

论文作者

Song, Wei, Li, Boya, Xue, Zihan, Li, Zhenzhen, Wang, Wenhao, Liu, Peng

论文摘要

缓存随机化最近已被恢复为对基于冲突的缓存侧通道攻击的有前途的防御。作为最新的两个实现,Ceaser-S和ScatterCache都声称使用随机偏斜的缓存阻碍了基于冲突的缓存侧通道攻击。不幸的是,我们的实验表明,攻击者可以轻松地在Ceaser-S选定的重置时期内找到可用的驱逐设置,并增加分区的数量而没有动态重新映射(例如ScatterCache),无法消除威胁。通过定量分析LLC中各种攻击所留下的访问模式,我们新发现了一些问题和随机缓存的假设和实现,这些问题也因基于冲突的缓存侧通道攻击而被忽略了。 但是,缓存随机化不是一个错误的希望,它是一种有效的防御,应在未来的处理器中广泛采用。新发现的问题对应于与现有的缓存随机化实现相关的缺陷,并且是可解决的。本文提出了几种新的防御技术。我们的实验表明,所有新发现的现有随机缓存的漏洞都固定在当前绩效预算之内。我们还认为,随机的设置缔合性缓存可以得到充分的加强,并且拥有比偏斜的同行在商业处理器中实际采用的更好的机会,因为它们对现有的缓存结构的大修较少。

Cache randomization has recently been revived as a promising defense against conflict-based cache side-channel attacks. As two of the latest implementations, CEASER-S and ScatterCache both claim to thwart conflict-based cache side-channel attacks using randomized skewed caches. Unfortunately, our experiments show that an attacker can easily find a usable eviction set within the chosen remap period of CEASER-S and increasing the number of partitions without dynamic remapping, such as ScatterCache, cannot eliminate the threat. By quantitatively analyzing the access patterns left by various attacks in the LLC, we have newly discovered several problems with the hypotheses and implementations of randomized caches, which are also overlooked by the research on conflict-based cache side-channel attack. However, cache randomization is not a false hope and it is an effective defense that should be widely adopted in future processors. The newly discovered problems are corresponding to flaws associated with the existing implementation of cache randomization and are fixable. Several new defense techniques are proposed in this paper. our experiments show that all the newly discovered vulnerabilities of existing randomized caches are fixed within the current performance budget. We also argue that randomized set-associative caches can be sufficiently strengthened and possess a better chance to be actually adopted in commercial processors than their skewed counterparts as they introduce less overhaul to the existing cache structure.

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