论文标题
使用HPCChallenge基准套件的参数化Opencl改编评估FPGA加速器性能
Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of the HPCChallenge Benchmark Suite
论文作者
论文摘要
FPGA发现在数据中心应用程序中的采用增加了，因为新一代的高级工具已经可用，这显着减少了FPGA加速器的开发时间，并且仍然提供了高质量的结果。但是，没有可用的高级基准套件，可以专门比较HPC应用程序的FPGA体系结构，编程工具和库。 为了填补这一空白，我们开发了用于Xilinx和Intel FPGA的HPCC基准套件的基于OPENCL的开源实现。该基准可以用于分析FPGA设备，卡和开发工具流的当前功能，跟踪随时间的进步，并指出HPC域中FPGA加速的特定困难。此外，基准文档已验证的性能优化模式。我们将继续优化新一代FPGA和设计工具的基准，并鼓励积极参与为社区创建有价值的工具。
FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high quality of results. There is however no high-level benchmark suite available which specifically enables a comparison of FPGA architectures, programming tools and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards and development tool flows, track progress over time and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community.
