论文标题
aCOTFPGA：基于FPGA系统的基于ASIC的近似算术组件
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems
论文作者
论文摘要
关于ASIC的近似电路（AC）的发展，已经进行了丰富的研究。但是，先前的研究表明，基于ASIC的ACS在基于FPGA的加速器中提供了不对称的增长。因此，对于ASIC的AC可能是FPGA的AC可能不是帕累托最佳的AC。在这项工作中，我们介绍了使用机器学习模型来减少探索时间来分析基于ASIC的最新ACs以确定帕托托（Pareto）最佳的基于FPGA的AC的集合。我们还进行了一个案例研究，以说明通过在最先进的自动化框架中部署这些帕累托最佳的基于FPGA的AC来获得的好处，以系统地生成帕累托最佳的近似加速器，这些加速器可以在基于FPGA的系统中部署，以实现高性能或低功能消耗。
There has been abundant research on the development of Approximate Circuits (ACs) for ASICs. However, previous studies have illustrated that ASIC-based ACs offer asymmetrical gains in FPGA-based accelerators. Therefore, an AC that might be pareto-optimal for ASICs might not be pareto-optimal for FPGAs. In this work, we present the ApproxFPGAs methodology that uses machine learning models to reduce the exploration time for analyzing the state-of-the-art ASIC-based ACs to determine the set of pareto-optimal FPGA-based ACs. We also perform a case-study to illustrate the benefits obtained by deploying these pareto-optimal FPGA-based ACs in a state-of-the-art automation framework to systematically generate pareto-optimal approximate accelerators that can be deployed in FPGA-based systems to achieve high performance or low-power consumption.
