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In this paper, we present a theoretical analysis of different integrating front-ends employed in broad-band communications through \textit{lossy} channels. Time-domain receivers for broad-band communication typically deal with large integrated noise due to its high bandwidth of operation. However, unlike traditional wireline systems that are typically not noise-limited, channels with high channel-loss render the input signal swing to be very small imposing several challenges in RX design as the circuits operate in the noise-limited regime. This simultaneous high integrated noise and low signal-swing limits the maximum achievable data-rate for a target bit-error-rate (BER) and deteriorates the energy-efficiency of the RX. In this work, transient, noise and gain performance of different standard signaling blocks have been obtained with closed-form expressions and are validated through spice-simulations. Multi-integrator cascade has been proposed which provides significant gain with relatively lower power consumption than the standard gain elements. Also, maximum achievable data-rate and optimum energy efficiency for different channel losses have been obtained theoretically for different architectures revealing their advantages and limitations. All the pertaining circuits have been designed in 65 nm CMOS process with a 1 V supply voltage.