论文标题
Brainscales神经形态硬件系统的验证和设计方法
Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System
论文作者
论文摘要
本文介绍了针对Brainscales-2 65nm ASIC的设计开发的验证和实施方法。第二代Brainscales芯片是混合信号设备，在完整的类似神经形态电路和两个通用微处理器（PPU）之间，具有SIMD扩展，可在芯片学习和可塑性之间进行紧密耦合。介绍了用于自动分析和预先拍摄的校准，对高度参数化的模拟神经元和Synapse电路以及用于数字逻辑和软件堆栈的硬件软件共同开发的模拟方法。全库神经形态部分和PPU之间的神经形态电路的加速操作和高度平行的数字数据总线需要自定义方法，以关闭接口处的数字信号时间。突出显示了标准数字物理实施设计流的新型扩展。我们介绍了最初包含512个神经元和130K突触的全尺寸Brainscales-2 ASIC的早期结果，证明了这些方法的成功应用。一个应用示例说明了Brainscales-2混合可塑性体系结构的全部功能。
This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Accelerated operation of neuromorphic circuits and highly-parallel digital data buses between the full-custom neuromorphic part and the PPU require custom methodologies to close the digital signal timing at the interfaces. Novel extensions to the standard digital physical implementation design flow are highlighted. We present early results from the first full-size BrainScaleS-2 ASIC containing 512 neurons and 130K synapses, demonstrating the successful application of these methods. An application example illustrates the full functionality of the BrainScaleS-2 hybrid plasticity architecture.
