论文标题
低功率数字信号处理的新近似乘数
New Approximate Multiplier for Low Power Digital Signal Processing
论文作者
论文摘要
在本文中，提出了低功率乘数。所提出的乘数利用了常规修改的展位乘数上的破碎阵列乘数近似方法。此方法将乘数的总功耗降低了58％，而产出准确性的成本较小。就功耗和准确性而言，将提出的乘数与其他近似乘数进行了比较。此外，为了更好地评估所提出的乘数效率，它已用于设计30-TAP的低通fir滤波器，并将功耗和精度与带有常规摊位乘数的过滤器进行比较。模拟结果表明，输出SNR的功率仅为0.4dB的成本下降17.1％。
In this paper a low power multiplier is proposed. The proposed multiplier utilizes Broken-Array Multiplier approximation method on the conventional modified Booth multiplier. This method reduces the total power consumption of multiplier up to 58% at the cost of a small decrease in output accuracy. The proposed multiplier is compared with other approximate multipliers in terms of power consumption and accuracy. Furthermore, to have a better evaluation of the proposed multiplier efficiency, it has been used in designing a 30-tap low-pass FIR filter and the power consumption and accuracy are compared with that of a filter with conventional booth multipliers. The simulation results show a 17.1% power reduction at the cost of only 0.4dB decrease in the output SNR.
