论文标题
RVCorep：五阶段管道的优化RISC-V软处理器
RVCoreP : An optimized RISC-V soft processor of five-stage pipelining
论文作者
论文摘要
RISC-V是一种基于RISC的开放式和忠诚度无教学套件的体系结构，该体系结构自2010年以来已开发，可用于FPGA的具有成本效益的软处理器。 RISC-V中设置的基本32位整数指令定义为RV32I，足以支持操作系统环境和嵌入式系统的诉讼。在本文中，我们提出了一个名为RVCorep的优化RV32I软处理器，该软处理器采用了五阶段管道。处理器应用三种有效的优化方法来提高工作频率。这些方法是指令提取单元优化，包括管道的分支预测机制，ALU优化以及数据记忆输出的数据对齐和签名扩展优化。我们在Verilog HDL中实现RVCorep，并使用Verilog模拟和实际的Xilinx Atrix-7 FPGA板验证行为。我们评估IPC（每个周期说明），操作频率，硬件资源利用率和处理器性能。从评估结果中，我们显示RVCorep与Vexriscv相比，RVCOREP的性能提高了30.0％，这是从某些相关工作中选择的高性能和开源RV32I处理器。
RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. The processor applies three effective optimization methods to improve the operating frequency. These methods are instruction fetch unit optimization including pipelined branch prediction mechanism, ALU optimization, and data alignment and sign-extension optimization for data memory output. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.
