论文标题
四维拓扑绝缘子的电路实施
Circuit Implementation of a Four-Dimensional Topological Insulator
论文作者
论文摘要
拓扑绝缘子的分类预测了在实际材料中无法发生的高维拓扑阶段的存在，因为这些阶段仅限于三个或更少的空间维度。我们使用电路来实验实施四维（4D）拓扑晶格。晶格维度是通过电路连接建立的，而不是通过映射到较低维系统的。在晶格的三维表面上，我们观察到与非零第二个Chern数量但消失的第一个Chern数量相关的拓扑表面状态。 4D晶格属于对称级AI，它指的是时间反转和无自旋系统，没有特殊的空间对称性。 AI级在一到三个空间维度上是拓扑的，因此4D是实现此类拓扑绝缘体的最低维度。这项工作为使用电路探索高维拓扑模型铺平了道路。
The classification of topological insulators predicts the existence of high-dimensional topological phases that cannot occur in real materials, as these are limited to three or fewer spatial dimensions. We use electric circuits to experimentally implement a four-dimensional (4D) topological lattice. The lattice dimensionality is established by circuit connections, and not by mapping to a lower-dimensional system. On the lattice's three-dimensional surface, we observe topological surface states that are associated with a nonzero second Chern number but vanishing first Chern numbers. The 4D lattice belongs to symmetry class AI, which refers to time-reversal-invariant and spinless systems with no special spatial symmetry. Class AI is topologically trivial in one to three spatial dimensions, so 4D is the lowest possible dimension for achieving a topological insulator in this class. This work paves the way to the use of electric circuits for exploring high-dimensional topological models.
